The manufacture of semiconductor devices such as dynamic random access memories (DRAM), static random access memories (SRAM), microprocessors, and logic devices involves a number of complex processing steps. While great care is taken during processing to ensure the steps are identical between each manufacturing lot of wafers, variability between lots, between wafers within a lot, and between dice on a single wafer commonly occurs. This processing variability results in differences in electrical performance of completed semiconductor dice.
The functionality and electrical performance of each die is measured at probe. This testing occurs at the wafer level subsequent to wafer processing and before the wafer is diced to separate each die prior to packaging. During wafer testing various semiconductor dice are found to be fully functional, some are not functional and not repairable, while others are not functional but may be repairable, depending on their failure mode. For example, if one or more storage elements of a row or column of storage capacitors is nonfunctional, a row or column of functional storage capacitors may be substituted through the use of fuse or antifuse (fusible link) devices. The following US patents, each assigned to Micron Technology, Inc. and incorporated herein as if set forth in their entirety, describe the formation and use of antifuse devices: U.S. Pat. No. 6,108,260 issued Aug. 22, 2000; U.S. Pat. No. 6,088,282 issued Jul. 11, 2000; U.S. Pat. No. 6,087,707 issued Jul. 11, 2000; U.S. Pat. No. 5,345,110 issued Sep. 6, 1994; U.S. Pat. No. 5,331,196 issued Jul. 19, 1994; U.S. Pat. No. 5,324,681 issued Jun. 28, 1994; U.S. Pat. No. 5,241,496 issued Aug. 31, 1993; 5,110,754 issued May 5, 1992.
Antifuses are commonly fabricated with a structure similar to that of a capacitor. Two conductive electrical terminals are separated by a dielectric layer. An unprogrammed “off” state, in which the antifuse is fabricated, presents a high resistance between the antifuse terminals (i.e. the terminals are electrically isolated from each other). The antifuse may also be programmed to an “on” state in which a low resistance connection between the antifuse terminals is provided (i.e. the terminals are electrically coupled or connected). To program or “blow” an antifuse to the “on” state, a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals. When an antifuse device is programmed “on,” it is selected to replace a nonfunctional storage capacitor row or column with a functional row or column.
FIG. 1 depicts a simplified diagram of a conventional arrangement of antifuse devices and other supporting circuitry. To program an antifuse device, for example device AF(0) (antifuse 0), the proper fuse address is output to FA(0) (fuse address 0), which typically comprises 8 or more address bits. This activates the transistor coupled with FA(0). The bank comprising AF(0) is selected by activating BSEL(0) (bank select 0) which activates all transistors associated with the BSEL(0) signal. With both FA(0) and BSEL(0) activated, the lower plate of AF(0), depicted as a curved line, is tied to ground while the lower plates of the remaining antifuses, which likely number in the thousands, are not tied to ground. Finally, to program AF(0), PROG is taken to a “high” state which, through program circuitry, ties CGND to a selected high voltage, for example 7 volts, and sends a “low” state to transistor T1. The high voltage on CGND is maintained for a period of time required to blow the fuse, which is dependent on the voltage applied to CGND. The upper plate of AF(0), depicted as a straight line, as well as the upper plates of the remaining antifuses, therefore, have the programming voltage applied thereto. With a high voltage applied to the upper plate of AF(0) and the lower plate tied to ground, the dielectric interposed between the two plates breaks down and the resistance between two plates is decreased such that the plates, in effect, are shorted together. A column decoder (not depicted) redirects the address from the nonfunctional column (not depicted) to the redundant column RC(0) associated with AF(0). Thus the antifuse latch AFUSE LATCH (0) associated with AF(0) is activated during operation of the memory device on powerup, and the redundant column RC(0) associated with AF(0) replaces a nonfunctional column. A similar arrangement is implemented to replace a nonfunctioning row with a redundant row.
As stated above, when the device is in program mode (PROG high), the Program Circuitry outputs a low to transistor T1 and a program voltage is applied to CGND. When the device is in normal operational mode, the Program Circuitry outputs a high to transistor T1 to tie CGND to ground for proper operation.
As semiconductor device manufacturing technology improves and storage capacitors continue to decrease in size, problems may result from the use of antifuse devices. One problem which may occur results from the voltage required to program the anti fuse. The voltage must be high enough to break down the dielectric between the antifuse plates in a reasonable amount of time. With the large number of antifuse devices which must be programmed with conventional memory devices, often numbering in the thousands, the voltage must be maintained at a fairly high level. As the feature size of semiconductor devices decreases with future device generations, the voltage required to program the antifuse may exceed the junction breakdown voltage of transistor T1. Thus the optimum voltage applied to CGND to program the antifuse will not be obtained because any voltage above the breakdown voltage of T1 can bleed to the substrate and pull down the CGND network of devices. Further, a high voltage over an extended period of time may adversely affect other devices which have a common active area which need to be connected to the CGND node for normal operation.
After functional testing and device repair using row and/or column redundancy in a conventional device, fully functional devices are speed graded and otherwise tested. After wafer-level testing is completed, the semiconductor wafer is diced to singularize each semiconductor die from other dice. Each functional die is assembled, for example including attachment to a lead frame and encapsulation in plastic, while nonfunctional dice are discarded.
A semiconductor device such as a DRAM comprises various default configurations which may be altered before encapsulation using bond options. For example, devices are typically manufactured for a “by 1” (×1) data width, such that only one data out line (DQ) is active to supply one data bit for each read cycle. Before encapsulation, the data width for the device can be changed by wire bonding together a “bond option pad” to a lead frame lead finger which is also electrically coupled with VCC or GND to modify its configuration. By using these “bond options” the device data width may be modified to a ×8 configuration, a ×16 configuration, a ×32 configuration, etc. Thus the device is manufactured to function in one manner if no bond options are selected, and will function in another manner if one or more bond options are selected.
Thus with conventional devices the ball bond is a first end of a bond wire and is attached to a bond pad of the die. A second end of the bond wire is attached to a lead finger of the lead frame, then the lead finger and die are encapsulated or otherwise packaged. In use, the lead is electrically coupled with power or ground, which determines how the die functions. The functionality of the die, therefore, is determined by a source external to the die, as the die will function one way if the lead is coupled with power, and another way if it is coupled with ground. Whether the lead will be coupled with power or ground is determined before the wire bond is connected, but the actual functionality depends on whether the lead is connected with power or ground.
Various other device parameters are a function of their processing and cannot typically be modified. These include internal power bus configurations or connecting/disconnecting internal circuitry. In such cases different photolithography masks would typically be required to modify circuit behavior or to modify power busing architecture. Mask sets can be expensive, require several weeks to manufacture, and add to semiconductor device manufacturing costs.
A method and structure which overcomes the problems described above and which allows for the modification of semiconductor device parameters not previously selectable in a manner not previously available would be desirable.